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smolder
on Dec 17, 2023
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Intel, Samsung, and TSMC Demo 3D-Stacked Transisto...
That's only if you needed a signal to cross the whole chip in one cycle. There's no such limitation preventing a 1 foot wide chip from being filled with 5ghz cores on an appropriate ring bus.
Jensson
on Dec 17, 2023
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But then you have many cores. With 3d scaling you could make a bigger core and still have high hz.
winwang
on Dec 17, 2023
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something something quantum tunnelling for probabilistic FTL signalling (/s)
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