I think one of the interesting takeaways here should be that they have a 48 - 50nm "device pitch" which is to say the transistors are small in the XY plane there are pitch widths much larger than "5nm" or "3nm" (people familiar with chip production realize this but too often people who don't have a very deep understanding of chip production are mislead into thinking you can put down transistors 5nm apart from each other)
So from a density perspective, a perhaps 30 - 40% gain in overall number of transistors in the same space.
Looking at the Intel inverter design, it looks like if they were willing to double the depth they could come up with a really compact DRAM cell. A chiplet with 8 GB of ECC DDR memory on it would be a useful thing both for their processors and their high end FPGA architectures.
I think one of the interesting takeaways here should be that they have a 48 - 50nm "device pitch" which is to say the transistors are small in the XY plane there are pitch widths much larger than "5nm" or "3nm" (people familiar with chip production realize this but too often people who don't have a very deep understanding of chip production are mislead into thinking you can put down transistors 5nm apart from each other)
So from a density perspective, a perhaps 30 - 40% gain in overall number of transistors in the same space.
Looking at the Intel inverter design, it looks like if they were willing to double the depth they could come up with a really compact DRAM cell. A chiplet with 8 GB of ECC DDR memory on it would be a useful thing both for their processors and their high end FPGA architectures.