It's common where area or performance are paramount, since it performs better than an equivalent (binary) counter in silicon. The Numerically Controlled Oscillator in the Apple M1 that is used to generate audio sample rates uses an LFSR as its first stage clock divider, and the driver has to load the right LFSR initializer value directly. It was fun working that one out. They use an LFSR because the input clock is a rather fast 1GHz or so, and dividing that down requires a bit of optimization.
There are some 4-bit CPUs that use an LFSR as the program counter, so the ROM gets stored in pseudorandom order.
It's fun how the lowest tech chips and the highest tech chips both end up resorting to the same old techniques, isn't it? :)
I think I saw your tweet about getting nerd-sniped into figuring this out. Or was that another component?
What would be the reason for the pseudorandom ROM order? Just a side effect of the PC choice or deliberate?
sidenote: interesting that two sentences into your response I knew exactly what name I was going to see as the author. Thanks for the work you're doing and especially for documenting it. I've been reversing my old DSL-modem to pass time during lockdowns and since it's an obscure, asic based model it's highly educational to see you talk about figuring out things living on the hard/software boundary.
The pseudorandom ROM order is just a consequence of using an LFSR as a counter, since it counts in pseudorandom order.
I'm glad you enjoy what I'm doing! It's a lot of fun being able to work on a project like this, and I'm glad some of it is educational for other folks.
There are some 4-bit CPUs that use an LFSR as the program counter, so the ROM gets stored in pseudorandom order.
It's fun how the lowest tech chips and the highest tech chips both end up resorting to the same old techniques, isn't it? :)